As network chips evolve, the need for handling more and more ports has increased. Adding more ports in a network chip often requires internal parallelism, where a portion of the traffic from each port is handled on a separate pipe. By creating more pipes, more ports can be added without causing the internal frequency of the network chip to be increased. However, increasing the number of ports inside the network chip causes problems in logic where states need to be maintained on a per port basis. For example, if the number of ports on the network chip is 128 and the number of pipes on the network chip is 8, then each pipe handles 16 of the 128 ports. Each of these ports is typically given a unique port number, which allows them to be identified. To represent these ports, an eight bit number is used. The eight bit number can represent a total of 256 ports. State space is 256 entries per pipe to store state information of 16 ports. As such, only a small subset of the state space is used. As the number of ports on a network chip increases, so does the state space per pipe. As the state space per pipe increases, so does the total logic on the network chip. It is inefficient to allocate this much state space since much of the state space is sparse.